1 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com edi8f81024c aug. 2001 rev. 8 eco #14552 the edi8f81024c is a 8mb cmos static ram based on eight 128kx8 static rams mounted on a multi-layered epoxy laminate (fr4) substrate. a version featuring low power with data retention (edi8f81024lp) is also available. the edi8f81024c is offered in a double sided, 36 pin single-in- line package (sip). surface mount sip technology is a cost effective solution to very high packing density requirements. all inputs and outputs are ttl compatible and operate from a single 5v supply. fully asynchronous, the edi8f81024c re- quires no clocks or refreshing for operation. pin configurations and block diagram pin names features ? 1024kx8 bit cmos static ? random access memory ? access times 70 thru 100ns ? data retention function (edi8f81024lp) ? ttl compatible inputs and outputs ? fully static, no clocks ? high density packaging ? 36 pin sip, no. 62 ? single +5v (10%) supply operation 1megx8 static ram cmos, module description a?-a19 address inputs e chip enable w write enable g output enable dq?-dq7 common data input/output vcc power (+5v10%) vss ground nc no connection
2 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com edi8f81024c aug. 2001 rev. 8 eco #14552 absolute maximum ratings* recommended dc operating conditions dc electrical characteristics *typical: ta = 25c, vcc = 5.0v capacitance truth table (f=1.0mhz, vin=vcc or vss) these parameters are sampled, not 100% tested. ac test conditions *stress greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. (note: for tehqz,tghqz and twlqz, cl = 5pf) voltage on any pin relative to vss -0.5v to 7.0v operating temperature ta (ambient) commercial 0c to +70c industrial -40c to +85c storage temperature plastic -55c to +125c power dissipation 1 watt output current 20 ma parameter sym min typ max units supply voltage vcc 4.5 5.0 5.5 v supply voltage vss 0 0 0 v input high voltage vih 2.2 -- 6.0 v input low voltage vil -0.3 -- 0.8 v input pulse levels vss to 3.0v input rise and fall times 5ns input and output timing levels 1.5v output load 1ttl, cl =100pf parameter sym conditions min typ* max units operating power icc1 w, e = vil, ii/o = 0ma, -- 80 130 ma supply current min cycle standby (ttl) power icc2 e 3 vih, vin vil -- 40 90 ma supply current vin 3 vih full standby power icc3 e 3 vcc-0.2v c -- 10 20 ma supply current (cmos) vin 3 vcc-0.2v or lp -- 400 950 a vin 0.2v input leakage current ili vin = 0v to vcc -- -- 10 a output leakage current ilo v i/o = 0v to vcc -- -- 10 a output high voltage voh ioh = -1.0ma 2.4 -- -- v output low voltage vol iol = 2.1ma -- -- 0.4 v g e w mode output power x h x standby high z icc2, icc3 h l h output deselect high z icc1 l l h read dout icc1 x l l write din icc1 parameter sym max unit input capacitance (except dq pins) ci 58 pf capacitance (dq pins) cd/q 43 pf input (e) control lines cc 10 pf input (w) line (g) cw 60 pf
3 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com edi8f81024c aug. 2001 rev. 8 eco #14552 ac characteristics read cycle read cycle 2 - w high read cycle 1 - w high, g, e low note: parameter guaranteed, but not tested. symbol 70ns 85ns 100ns parameter jedec alt. min max min max min max units read cycle time t avav trc 70 85 100 ns address access time tavqv taa 70 85 100 ns chip enable access time telqv tacs 70 85 100 ns chip enable to output in low z (1) telqx tclz 5 5 5 ns chip disable to output in high z (1) tehqz tchz 30 35 40 ns output hold from address change tavqx toh 3 3 3 ns output enable to output valid tglqv toe 40 45 50 ns output enable to output in low z (1) tglqx tolz 0 0 0 ns output disable to output in high z(1) tghqz tohz 30 35 40 ns address 1 address 2 tavav data 1 data 2 tavqv tavqx a q tghqz telqv telqx e g q tehqz a tavav tglqv tglqx tavqv
4 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com edi8f81024c aug. 2001 rev. 8 eco #14552 ac characteristics write cycle write cycle 1 - w controlled note 1: parameter guaranteed, but not tested. symbol 70ns 85ns 100ns parameter jedec alt. min max min max min max units write cycle time tavav twc 70 85 100 ns chip enable to end of write telwh tcw 65 70 80 ns teleh tcw 65 70 80 ns address setup time tavwl tas 0 0 0 ns tavel tas 0 0 0 ns address valid to end of write tavwh taw 65 70 80 ns taveh taw 65 70 80 ns write pulse width twlwh twp 65 70 80 ns twleh twp 65 70 80 ns write recovery time twhax twr 0 0 0 ns tehax twr 0 0 0 ns data hold time twhdx tdh 0 0 0 ns tehdx tdh 0 0 0 ns write to output in high z (1) twlqz twhz 0 30 0 35 0 40 ns data to write time tdvwh tdw 30 35 40 ns tdveh tdw 30 35 40 ns output active from end of write (1) twhqx twlz 5 5 5 ns e a tavav telwh tavwh twlwh tavwl twhax w high z data valid twlqz twhqx tdvwh twhdx q d
5 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com edi8f81024c aug. 2001 rev. 8 eco #14552 write cycle 2 - e controlled data retention e controlled data retention characteristics note 1: parameter guaranteed, but not tested. * read cycle time characteristic sym test conditions vdd min typ max unit 70c 85c data retention voltage vdd vdd = 0.2v 2 -- -- -- v data retention quiescent current iccdr e 3 vdd -0.2v 2v -- 25 300 400 a vin 3 vdd -0.2v 3v -- 50 450 550 a chip disable to data retention time (1) tcdr or vin 0.2v 0 -- -- -- ns operation recovery time (1) tr t avav* -- -- -- ns a tavel high z tavav teleh e taveh tehax w twleh tehdx tdveh q data valid d vcc tr data retention mode e tcdr e 3 vdd-0.2v vdd 4.5v 4.5v
6 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com edi8f81024c aug. 2001 rev. 8 eco #14552 package description package no. 62: 36 pin single-in-line package note: to order an industrial grade product substitute the letter c in the suffix with the letter i, eg. edi8f81024c70bsc becomes edi8f81024c70bsi. ordering information standard power low power with speed package data retention (ns) no. edi8f81024c70bsc edi8f81024lp70bsc 70 62 edi8f81024c85bsc edi8f81024lp85bsc 85 62 edi8f81024c100bsc EDI8F81024LP100BSC 100 62 all dimensions are in inches
|
